Semiconductor devices are used in a large number of electronic devices, such as computers, cell phones, and others. Semiconductor devices comprise integrated circuits that are formed on semiconductor wafers by depositing many types of thin films of material over the semiconductor wafers, and patterning the thin films of material to form the integrated circuits. Integrated circuits include field-effect transistors (FETs), such as metal oxide semiconductor (MOS) transistors.
One of the goals of the semiconductor industry is to continue shrinking the size and increasing the speed of individual FETs. To achieve these goals, three dimensional (3-D) or non-planar transistor structures such as fin FETs (FINFETs), multiple gate transistors, or gate all around transistors are being investigated for use in sub 22 nm transistor nodes. Such transistors not only improve areal density, but also improve gate control of the channel.
However, fabrication of these non-planar FETs is complex and requires overcoming a number of challenging problems. One of the challenges is forming metal semiconductor contacts with low contact resistance. As at least one of the source or the drain contacts is composed partially or fully of a metal silicide, the Schottky barrier height between the source/drain region and the metal silicide needs to be reduced. A method of reducing the Schottky barrier height involves increasing the doping level of the surface of the semiconductor being contacted. Traditional methods of doping the semiconductor involve implanting dopants into the surface of the semiconductor during or after source/drain implantation. Unlike planar structures, however, such implantation into non-planar structures does not produce uniform surface or near surface concentrations. Further, in non-planar structures, implantation leaves residual defects that may result in poor silicide formation or result in leakage currents.
Accordingly, what is needed in the art are structures and methods of fabrication thereof withlow resistance contacts for non-planar semiconductor structures.
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale.